library verilog;
use verilog.vl_types.all;
entity Summodule is
    port(
        E               : in     vl_logic_vector(3 downto 0);
        D               : in     vl_logic_vector(3 downto 0);
        C               : in     vl_logic_vector(3 downto 0);
        M               : in     vl_logic;
        F               : out    vl_logic_vector(3 downto 0);
        AEB             : out    vl_logic
    );
end Summodule;
